Join Amit Gupta, VP and GM of Solido Custom IC and Siemens EDA AI, as he unveils the new Siemens EDA AI System transforming semiconductor design. This comprehensive generative and agentic AI system combines best-in-class LLMs, an EDA-specific data lake, and sophisticated RAG methodologies to meet the demands of today's complex SoC designs. Experience how this purpose-built system unlocks massive productivity gains across the Siemens EDA portfolio and ushers in the next era of EDA.

Join this session to learn how AI-powered Solido Simulation Suite is revolutionizing SPICE verification for modern semiconductor design. See a demo of new Solido Sim generative and agentic AI in action and learn how seamless integration with Siemens EDA tools enables comprehensive IC verification for next-generation technologies.

Discover in this session how our integrated solution combines AI-accelerated Solido FastSPICE with Symphony mixed-signal technology to transform IC verification. See firsthand how this powerful combination tackles complex analog-digital interactions across all design levels - from IP blocks to full-chip implementations - enabling faster, more comprehensive verification for modern IC designs.

Discover how Solido Design Environment's AI-powered technology revolutionizes SPICE-level verification for today’s IC designs. See a demo of new generative and agentic AI capabilities across the workflow, and learn how Additive Learning technology achieves 3-20X speedup in variation-aware verification across multiple sigma targets, resulting in faster turn-around time and less compute consumption.

Join this session to explore how Solido Characterization Suite delivers a comprehensive flow for standard cell library development. See how AI-enabled liberty validation, generation, and smart IP selection ensure optimal PPA metrics. Learn how this data-driven approach accelerates SoC design cycles and see a demo of new generative and agentic AI capabilities that enhance the suite.

Join this session to learn how Solido IP Validation Suite ensures comprehensive IP validation across multiple design views. See how Solido Crosscheck and IPdelta detect inconsistencies early, prevent costly errors, and enable reliable IP releases. Don't miss the demo of new generative and agentic AI capabilities for Solido IP Validation Suite.

Join this session to learn how Solido IP Validation Suite ensures comprehensive IP validation across multiple design views. See how Solido Crosscheck and IPdelta detect inconsistencies early, prevent costly errors, and enable reliable IP releases. Don't miss the demo of new generative and agentic AI capabilities for Solido IP Validation Suite.

本場將剖析次世代線路圖繪製軟體 Allegro System Capture 內建 Audit Schematic 與 Analyzes electrical stress 分析的強大功能，滿足設計上對Schematic DRC與Component Derating檢查的進階需求，引領使用者完成產品設計可靠度的最佳化。

Allegro X AI 技術運用雲端的多重擴展特性，以全新技術讓 PCB 佈局、鋪銅以及關鍵訊號佈線流程自動化，並整合初步的訊號與電源完整性分析。讓設計者運用 AI 智能，大幅縮短 PCB 設計時程，本場將帶你一探究竟。

全新 Cadence OrCAD X 版本，整合電路圖、佈局、分析、設計協作與資料管理，更融合智慧科技元素，為你打造更高效、聰明的電子設計流程。22.1 最新版更新部分，不管是在 Constraint Manager 可以有更精細的設定項目，全新 3D 畫面更為簡明，或是針對差分訊號的 Via Structure 可以快速去切換的功能等等，各種快速提升設計效率功能的實用技法，將在本場中一次傳授給你。

Graser 為了解決 RD 及 Layout 人員在設計上所花費的龐大時間與人力，持續致力於開發各式各樣快捷簡便的輔助工具，試圖解決產品在開發時間越來越被壓縮的困擾，於是 GraserWARE 的產品誕生了。 本場將分享 GraserWARE 最新快捷應用要領。

在本次講演中將透過比較 Intel 與 AMD 公板的 DDR5 佈局走線差異並藉由 Cadence Sigrity PowerSI/Allegro TopXp 萃取信號 S 參數與眼圖模擬，探索 DDR5 佈局走線最佳化的方向。

本場將以 Celsius 暫態模擬與相關演算法進行熱管理分析優化，及熱應力分析與相關整合分析流程介紹。

本場將解析如何以 Optimality 結合 Clarity 進行 RF/SI 之 S 參數最佳化，並透過 Topxp 進行 Eye-diagram 最佳化。