Abstract: There is tremendous increase in information traffic with the digital transformation of businesses, demanding fast access to data. Data transfer speeds are reaching new highs for short and long reach transceiver applications requiring innovative and advanced signal modulation techniques. Multi-die chips are the new norm for better yield and customization, in-turn forcing increased cross-die communication. Analog components within are required to operate with lesser margin, while needing to be area and power efficient. Precision functionality thus becomes key for all components on chip, and deviation from it can lead to additive detrimental effects, including catastrophic failures.

For analog verification, a foundry-certified SPICE simulator that can handle large netlists efficiently and accurately is a must to ensure silicon correlation. Designers requires a reliable toolset to analyze with transient, small-signal, multi-simulations, RF, aging and reliability analyses with flexible use models to ensure design robustness. Superior S-parameter handling of many, and large N-ports is becoming crucial. The pressure to design more ICs with aggressive time-to-market goals further imposes the need for a high-performance simulator.

Introducing an advanced AFS eXTreme (AFS XT)! In this session, we will showcase AFS XT’s versatility as a point tool as well as an integrated EDA flow solution, and how it can be used to solve your verification challenges of complex IC design.

Abstract: Today’s semiconductor designs incorporate power, performance, and area improvements to realize the next generation of IC designs. For these designs, the increase in design scale and complexity means IC verification strategies must evolve to cover exponentially more scenarios than before.

Variation-aware SPICE-level verification of designs over process, voltage, and temperature (PVT) corners as well as local variation mismatch is a critical step that ensures quality and robustness of final silicon.

This session discusses how to achieve high accuracy and coverage for variation-aware verification at 3, 4, 5 and 6+ sigma targets, using Solido Variation Designer to maximize the utilization of simulation budgets to achieve accuracy and coverage targets, while improving runtime by orders of magnitude.

Abstract: Mixed-signal verification is an indispensable aspect of modern System-on-Chips (SoCs) developed for applications such as AI, HPC, Automotive, and IoT. These domains require seamless integration of analog and digital components in a single SoC to achieve reliable and high-performance systems. Verifying such systems is a daunting task.

The “Shift Left” verification trend has been around for over a decade. The idea is to verify early in the design cycle resulting in better products, fewer re-spins, faster time to market, and lower cost. Shift Left is driving the adoption of new verification methodologies. However, when it comes to mixed signal designs, it gets a bit complicated due to the complexity of interactions between analog and digital. Most of the digital verification technologies have not been extended to verify mixed signal design. This could be due to lack of knowledge, lack of standards or lack of EDA technologies to support these methodologies in mixed-signal domain.

In this session we will learn how our latest solution Symphony Pro can address these verification challenges and help you improve your verification productivity significantly.

Abstract: Correct and accurate .libs are a fundamental requirement for a successful production tape-out. However, detecting all issues in .libs is almost impossible without the correct tools. These undetected errors in .libs directly lead to valuable engineering time spent debugging design closure and convergence issues, as well as potential for silicon failure.

In addition, to ensure product reliability across all target operating conditions, design and signoff teams require .libs characterized at many process, voltage and temperature (PVT) corners. Characterizing additional PVT corners involves significant time and effort.

In this session, we show how AI methods can be leveraged to significantly speed up time-to-tapeout and reduce production errors for digital designs. We discuss how Solido Characterization Suite verifies accuracy and correctness of .libs and produces .libs at new PVT corners 100X faster than traditional methods, resulting in better quality timing libraries and faster, more predictable tape-out schedules.

Abstract: IP validation is a key factor in determining time-to-market and silicon success. To be correctly integrated into chip-level or block-level designs, design IP must be validated for multiple views (logical, physical, timing, SPICE, etc.) for consistency and correctness. This may require days or weeks per iteration by both IP production and integration teams. IP issues discovered at chip-level signoff or after tape-out may result in require costly ECO iterations or re-spins.

Solido Crosscheck provides a complete QA framework for the validation of all IP, regardless of type or technology, covering all backend and frontend design views for IP production and integration workflows. It also enables IP suppliers and integrators to align on validation requirements and results through a common QA exchange deck, ensuring that all checking and reporting standards are accurately captured throughout the IP supply chain.

In this session, we will discuss common IP issues discovered, how Solido Crosscheck helps check for these issues, and streamlines validation cycles and reporting between IP suppliers and integration teams.