Pradeep Thiagarajan is a Director of Product Management at Siemens EDA for Custom Simulation products, including SPICE, fast SPICE, and Mixed-signal technologies. He has over 23 years of experience in the Semiconductor industry spanning roles in Analog IP design, SoC program management, and EDA product management and marketing. He is currently translating his IC engineering experiences into the EDA software industry to further verification technology. He has an M.S. in Electrical Engineering from University of Minnesota and holds 41 US patents.

Jayne Alexander is a technical product manager for Solido Design Environment at Siemens EDA, with 4+ years of experience as an application engineer supporting top semiconductor companies on their verification methodologies. Jayne graduated from the University of Saskatchewan's Computer Science Department with a degree in Bioinformatics.

Sathish currently leads the product management and marketing organization for Custom IC Verification (CICV) division at Siemens. Sathish is an experienced product leader with over 20+ years of experience in EDA industry. Sathish’s focus is on bringing value to semiconductor ecosystem through innovative solutions. Sathish is proficient in scaling product portfolio growth and expansion of market share/revenue through relentless focus on data-based execution and thought leadership.

Prior to Siemens, Sathish held various product management, strategic business development and corporate development roles for Cadence Design Systems and Synopsys. Sathish received his BS in Electronics & Communication from University of Madras, MS in computer engineering from University of Alabama & MBA from UC Berkeley- Hass School of Business.

Dr. Hsu has 20-year CMOS analog circuit design experience and 10-year EDA system integration experience. Besides CMOS integrated circuit design, Dr. Hsu also has much MEMS and heterogeneous integration experience, and his PhD. research is semi-passive smart contact lens platform for eye disease diagnosis.

Jason has over 28 years of semiconductor experience in PDK, IP FE/BE model, and design methodology, with 24 years in R&D team management and with 8 patents. He is currently with Faraday Technology, focusing on advanced IP and design flows.

Delbert Liao is a Principal MTS at Rivos, Inc., responsible for custom IP design and third-party IP integration. He has 15 years of experience in the semiconductor industry. Before joining Rivos in May 2022, he spent nearly ten years at Augentix and MediaTek, focusing on analog design, SI/PI, and packaging design. Delbert holds a master's degree from National Tsing Hua University, Taiwan.

Chiang-Hsiang Liao is a Senior MTS at Rivos, Inc., responsible for custom circuit design, especially standard cell library. He has 10 years of experience in the semiconductor industry. Before joining Rivos in Sep. 2023, he worked as a designer at Faraday, Novatek, TSMC, and Digwise, focusing on standard cell design and design flow development. Chiang-Hsiang holds a master's degree from National Sun Yat-sen University, Taiwan.