Join Sathish Balasubramanian, Senior Director of Product, as he unveils the new Siemens EDA AI System transforming semiconductor design. This comprehensive generative and agentic AI system combines best-in-class LLMs, an EDA-specific data lake, and sophisticated RAG methodologies to meet the demands of today's complex SoC designs. Experience how this purpose-built system unlocks massive productivity gains across the Siemens EDA portfolio and ushers in the next era of EDA.

Learn how Veloce proFPGA CS platform can enable you to shorten prototyping bring-up time and effort. During this presentation we will introduce how Veloce Prototyping implementation software is delivering best-in class automation to model and partition prototypes targeting latest FPGA on the market.

Prototyping verification has become increasingly critical as SoC designs grow in complexity and verification cycles shorten. However, traditional FPGA-based prototyping often faces challenges such as manual partitioning efforts, long bring-up cycles, and limited debug visibility. This paper introduces how the proFPGA CS platform accelerates prototyping verification through its automated partitioning engine and advanced debug capabilities. The Auto-Partition feature minimizes manual work and reduces partitioning errors by intelligently distributing logic across FPGAs, while the integrated debug framework enables fast signal tracing, iterative updates, and high-visibility analysis during system execution. Experimental results show that the proposed flow significantly shortens iteration time, improves development efficiency, and enhances overall verification quality. This approach offers an effective solution for teams seeking to optimize their prototyping workflow and accelerate time-to-market.

Discover how Solido Design Environment's AI-powered technology revolutionizes SPICE-level verification for today’s IC designs. See a demo of new generative and agentic AI capabilities across the workflow, and learn how Additive Learning technology achieves 3-20X speedup in variation-aware verification across multiple sigma targets, resulting in faster turn-around time and less compute consumption.

Tired of fragmented verification flows and inconsistent results across your design cycle? This isn't just about VIP; it's about a holistic verification ecosystem that delivers absolute consistency and unparalleled efficiency. We'll demonstrate how this game-changing unified kernel ensures seamless correlation and high-fidelity results across every stage

The automotive industry is undergoing a structural transformation driven by the emergence of the Software-Defined Vehicle (SDV). OEMs and suppliers must deliver advanced compute performance, shorten design cycles, manage increasing architectural complexity, and support long-term over-the-air updates—all while hardware development remains slow, costly, and inflexible. Traditional sequential processes, where software development waits for silicon or prototype boards, no longer meet market demands. Siemens PAVE360 provides a comprehensive digital-twin platform that fundamentally reshapes this development model. It enables “shift-left” practices, allowing OEMs, Tier-1s, Tier-2s, and IP providers to explore architectures, design hardware, and develop software 12–18 months before physical hardware exists. By integrating mixed-fidelity models, real hardware, virtual ECUs, sensors, actuators, and simulation data, PAVE360 delivers a full-system view essential for SDV programs.

The successful integration of Innexis DevPro and Innexis Ana marks a paradigm shift in how high-performance modeling and analytics are utilized within the complex domain of Electronic Design Automation (EDA). By adhering to the Shift-Left principle, we have fundamentally reorganized the design verification process, moving critical analysis functions from a reactive, late-stage activity to a proactive, early-stage capability.

本場將剖析次世代線路圖繪製軟體 Allegro System Capture 內建 Audit Schematic 與 Analyzes electrical stress 分析的強大功能，滿足設計上對Schematic DRC與Component Derating檢查的進階需求，引領使用者完成產品設計可靠度的最佳化。

Allegro X AI 技術運用雲端的多重擴展特性，以全新技術讓 PCB 佈局、鋪銅以及關鍵訊號佈線流程自動化，並整合初步的訊號與電源完整性分析。讓設計者運用 AI 智能，大幅縮短 PCB 設計時程，本場將帶你一探究竟。

全新 Cadence OrCAD X 版本，整合電路圖、佈局、分析、設計協作與資料管理，更融合智慧科技元素，為你打造更高效、聰明的電子設計流程。22.1 最新版更新部分，不管是在 Constraint Manager 可以有更精細的設定項目，全新 3D 畫面更為簡明，或是針對差分訊號的 Via Structure 可以快速去切換的功能等等，各種快速提升設計效率功能的實用技法，將在本場中一次傳授給你。

Graser 為了解決 RD 及 Layout 人員在設計上所花費的龐大時間與人力，持續致力於開發各式各樣快捷簡便的輔助工具，試圖解決產品在開發時間越來越被壓縮的困擾，於是 GraserWARE 的產品誕生了。 本場將分享 GraserWARE 最新快捷應用要領。

在本次講演中將透過比較 Intel 與 AMD 公板的 DDR5 佈局走線差異並藉由 Cadence Sigrity PowerSI/Allegro TopXp 萃取信號 S 參數與眼圖模擬，探索 DDR5 佈局走線最佳化的方向。

本場將以 Celsius 暫態模擬與相關演算法進行熱管理分析優化，及熱應力分析與相關整合分析流程介紹。

本場將解析如何以 Optimality 結合 Clarity 進行 RF/SI 之 S 參數最佳化，並透過 Topxp 進行 Eye-diagram 最佳化。