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Customize and standardize your IC verification configuration

Srinivas Velivala Siemens EDA

In this paper, we focus on how design teams can use the Calibre Interactive tool to set up and initiate runs for physical, circuit, and reliability verification, as well as parasitic extraction. The correct environment configuration ensures designers are optimizing the accuracy and performance of their signoff verification flows. The Calibre Interactive interface provides an easy-to-use GUI that allows CAD engineers to create and maintain standardized and customized runsets for different process nodes and design styles. Designers can then use the same GUI to quickly and consistently initiate verification runs from within their familiar IC design environment.


Resolving cell name conflicts for efficient layout hierarchy

Dennis Joseph Siemens EDA

Duplicate cell names across multiple IP in an SoC can result in unexpected layout results at the full-chip level, larger file sizes, and the inability to run layout verification tools efficiently in hierarchical mode. The Calibre DESIGNrev tool provides a simple, efficient, automated solution for identifying, renaming, and reporting these cell name conflicts. The outcome is a clear and consistent design process, straightforward chip assembly, a clean and meaningful design hierarchy, faster EDA tool runtimes, and faster time to tapeout.


Accelerate time to market with Calibre nmLVS Recon technology: A new paradigm for circuit verification

Hend Wagieh Siemens EDA

One thing is clear…tapeouts are getting harder, and taking longer. As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS Recon tool enables design teams to rapidly examine dirty and immature designs to find and fix high-impact circuit errors earlier and faster, leading to an overall reduction in tapeout schedules and time to market.


Increase LVS verification productivity in early design cycles

Raghav Katoch Siemens EDA

With the innovative Calibre nmLVS Recon early verification tool, designers can run targeted short isolation analysis and debugging on blocks, macros and chips in early design phases. The Calibre nmLVS-Recon short isolation use model focuses on fast, efficient, prioritized short isolation and short paths debugging.


Net common resistance -Extraction is crucial to design reliability

Hossam Sarhan Siemens EDA

Accurately extracting and calculating the common resistance of interconnects within analog IC designs is fundamental for evaluating circuit reliability, particularly for noise and voltage drop analysis, and ESD protection verification. The Calibre PERC reliability solution provides a packaged common resistance check that simplifies and automates this technique, ensures accurate and efficient resistance measurements, and supports fast and accurate debugging of any errors detected.


The true costs of process node migration

John Ferguson Siemens EDA

Deciding when and how to make a process node transition is critical to business success. The solution that requires the least amount of total change – in the form of license configurations, required hardware resources, necessary tool qualifications, and adequate support infrastructure – will always be the most “inexpensive” option. Do you have all the information you need to make the right decision?