Turning 3DIC concepts into working designs requires tight alignment across architecture, packaging, and verification. This session introduces an integrated layout and verification design flow that helps teams assess feasibility early, manage stacking complexity, and accelerate the path from initial planning to production-ready designs.

As 2.5D and 3DIC designs continue to scale in both complexity and size, efficient layout implementation and smart use of automation have become critical to maintaining productivity. In this session, we will introduce the latest updates in Innovator3D IC Layout and explore how automation scripts can help streamline and accelerate the layout process in real design workflows.

Calibre 3DPERC extends the industry leading reliability verification solutions of Calibre PERC to 3D IC, across multiple dies and different process nodes. This solution provides the scalability to handle your most challenging 3D IC assemblies

A scalable analysis platform was introduced to provide a comprehensive solution for transistor-level power grid verification including reliabilty checking. Both static and dynamic EM/IR drop can be analyzed for 2.5D/3D design. / Calibre 3DThermal performs highly accurate and computationally efficient thermal analysis throughout the IC design flow. With Calibre 3DThermal, designers of 3DICs now have an integrated chip-package thermal co-design flow that spans early-stage feasibility analysis through to design sign-off.

This session provides a comprehensive overview of the latest enhancements to the Avery UCIe VIP within the Questa One verification platform. Specifically designed to address the complexities of advanced 3DIC protocol verification, the content covers the UCIe VIP's core features, testbench architecture, and practical implementation examples. Key technical capabilities are highlighted, including function support, callback features, and advanced debugging tools such as tracker files and waveform analysis. Furthermore, the session offers detailed testcase guidelines and outlines the technical support available to ensure a robust and efficient verification environment for next-generation designs.

Tessent Multi-Die is a cutting-edge solution designed to address the challenges associated with 2.5D, 3D, and 5.5D stack designs in advanced semiconductor packaging. As the demand for higher performance, integration, and miniaturization in modern electronic systems increases, traditional single-die chip designs are often insufficient. The Tessent Multi-Die solution enables the seamless integration of multiple dies within a single package, offering superior performance, reduced power consumption, and optimal space utilization. This approach leverages a comprehensive suite of advanced tools, including Tessent SSN, TestKompress, Boundary Scan, and IJTAG, to ensure high-quality testing, fault detection, and system-level verification. Together, these solutions enhance the overall yield, reliability, and manufacturability of multi-die stack designs, enabling the development of next-generation systems in areas such as telecommunications, artificial intelligence, and high-performance computing.