Figure 1Growth Comparison: Semiconductor, Packaging & Testing, and AI
Chip Advanced Packaging
Figure 2Global Data Center AI Chip Advanced Packaging Revenue Forecast
Figure 3Taiwanese Vendors' Data Center AI Chip Advanced Packaging Revenue
Forecast
Figure 4Definition: Data Center AI Chips ─ AI Accelerators
Figure 5Definition: Data Center AI Chip Advanced Packaging
Figure 6Megatrend 1: From Monolithic SoC to Chiplet Architecture
Figure 7Megatrend 2: From 2D to 2.5D/3D/3.5D IC Packaging
Figure 8Benefits of Advanced Packaging
Figure 9The Walls for Data Center AI Chips
Figure 10Advanced Packaging to Overcome The Barriers of Walls
Figure 11Evolution of Compute Performance (Speed x Density) per Reticle
From Process Node N28 to A16
Figure 12Data Center AI Chips and Their Advanced Packaging Solutions
Figure 13Global data center AI chip shipment forecast
Figure 14Data Center AI Chip Shipment CAGR 2024-2030
Figure 15Global Data Center AI GPU Shipment Forecast 2024-2030
Figure 16Nvidia AI GPU Roadmap & Specifications
Figure 17Data Center AI GPU Improvement: From Hopper to Rubin
Figure 18AMD AI GPU Roadmap & Specifications
Figure 19Global Data Center Application-specific AI Chip Shipment
Forecast 2024-2030
Figure 20Main Reasons for Adopting Custom AI Chips
Figure 21TPU Roadmap & Specifications
Figure 22TPU Evolution: Peak AI Inference Performance with FP8 Precision
Figure 23TPU Evolution: Peak TFLOPS Performance per Watt
Figure 24AWS AI Chip Roadmap & Specifications
Figure 25The Huawei Ascend AI Chip Roadmap
Figure 26Huawei Atlas SuperPod Roadmap and the Comparison to Nvidia Rack
Systems
Figure 27Global Data Center AI Server CPU Shipment Forecast
Figure 28AI Server CPU Specifications
Figure 29Global Data Center AI Networking Processor Shipment Forecast
Figure 30Nvidia Data Center Switch Roadmap Specifications
Figure 31Nvidia Data Center CPO Switches in 2026
Figure 32Broadcom Tomahawk Switch Roadmap Specifications
Figure 33GB200 NVL72 Compute Trays and Switch Trays
Figure 34Huawei CloudMatrix 384 System
Figure 35Forecast of 300mm Wafer Consumption for Data Center AI
Accelerators
Figure 36Forecast of Wafer Foundry Revenue for Data Center AI
Accelerators
Figure 37Number of Compute Dies per Package for Data Center High-End GPUs
and Custom AI Chips 2024-2030
Figure 38Global Data Center AI Chip Packaging Market Forecast (by
Technology)
Figure 39Global Data Center AI Chip Packaging Market Share (by
Technology)
Figure 40Taiwan Data Center AI Chip Packaging Market and Market Share
Forecast
Figure 41TSMC Data Center AI Chip Packaging Revenue and Market Share
Forecast
Figure 42TSMC's advanced packaging portfolio
Figure 43TSMC Data Center AI Chip Packaging Revenue Forecast ($B)
Figure 44ASEH Data Center AI Chip Packaging Revenue Forecast ($M)
Figure 45Powertech's Data Center AI Chip Packaging Revenue Forecast ($M)
Figure 46The Data Center AI Chips Supply Chain Overview
Figure 47CoWoS Technology Roadmap
Figure 48Comparison of CoWoS Family
Figure 49The Capability of TSMC CoWoS-L for Scaling-up System
Figure 50The Comparison between CoWoS and CoPoS
Figure 51Analysis of CoWoS Supply Chain
Figure 52Global Data Center-related CoWoS and CoWoS-like Wafer
Consumption Forecast
Figure 53Global Data Center AI Chip CoWoS/CoPoS-type Packaging Revenue by
Application
Figure 54SoIC with Finer Bonding Pitch and Extremely High Density
Figure 55The Performance of SoIC-X with Different Bond Pitches
Figure 56Applications of the SoIC and Similar 3D Stacking Technologies
Figure 57Evolution of Co-Packaged Optics(CPO)
Figure 58Benefits of AI Accelerators from 2.5D to 3.5D Packaging
Figure 59TSMC SoIC Capacity Forecast
Figure 60Forecast of SoIC and SoIC-like 3D Stacking Revenue for Data
Center AI Chips
Figure 61Revenue Forecast of SoIC and SoIC-like 3D Stacking for Global
Data Center AI Chips by Application
Figure 62Comparison of SoW-P with SoW-X
Figure 63SoW-X vs. CoWoS-L Improvement
Figure 64The Disruptive SoW-X and the Comparison to CoWoS Evolution
Figure 65Forecast of SoW Revenue in the Global Data Center AI Chip Market
Figure 66HBM Roadmap Projection through 2030
Figure 67Global HBM Packaging Revenue Forecast
Figure 68Timelines of Data Center AI Chip Packaging
Figure 69Implications of the Timelines
Figure 70The Technology Transition for Data Center AI Chip Advanced
Packaging
Figure 71New Competition Toward Advanced Packaging
Figure 72The Chip Platform Competition and Its Impact on Advanced
Packaging
Figure 73The Advanced Packaging Portfolio for Major Foundry/IDM Companies
Figure 74TSMC Data Center AI Chip Advanced Packaging Roadmap
Figure 75Intel Data Center/PC Advanced Packaging Roadmap
Figure 76Samsung Data Center AI Chip Advanced Packaging Roadmap
Figure 77The Packaging Portfolio of Chinese OSAT Vendors
Figure 78Top 3 Foundries/IDMs' Packaging Solution Comparison
Figure 79Emerging Competitive Landscape and Development Trends in
Advanced Packaging
Figure 80Top 5 Restrictions for China's AI Chip Development from the US
Government
Figure 81China Data Center AI Chip Supply Chain
Figure 82China Local-made Data Center AI Accelerator Shipment Forecast
Figure 83Comparison of the Growth Momentum of the Semiconductor Market,
Packaging Market, and Data Center AI Chip Advanced Packaging Market
Figure 84Three Main Growth Drivers for the Global Data Center AI Chip
Packaging Market
Figure 85Taiwanese Vendors' Data Center AI Chip Advanced Packaging
Revenue Forecast
